Altera FPGA Design for High Performance

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This course provides all necessary theoretical and practical know-how for advanced FPGA design through VHDL standard language.
The course goes into great depth and touches upon advanced design considerations, design problems and solutions, low power design, high frequency design, minimal area design, multiple clock domains and synchronization circuits, advanced use of PLL, advanced timing analysis, advanced state machine design, design optimal arithmetic circuits and much more.
The course combines 60% theory with 40% practical work in every meeting.
The practical labs cover most of the theory and also include practical digital design.
This course also enriches digital engineers with many years of experience.
Course Duration : 5 days
1. Write an efficient code to maximize FPGA architecture and synthesis tools utilization
2. Design pipeline circuits with an emphasis on latency and throughput
3. Solve timing closure issues and optimize critical paths
4. Employ advanced PLL configuration for different work modes
5. Design optimal arithmetic circuits with an emphasis on algorithms
6. Design generic building blocks to enhance reusability and maintainability
7. Design multi-clock domains and synchronization circuits for variety use cases
8. Design reliable reset circuits
9. Design state machines for high frequency and reliability
10. Design reliable asynchronous FIFO using design optimization techniques
Hardware engineers who develop FPGAs and would like to enhance their skills, in order to understand synthesis limitations, to acquire better expertise on avoiding digital problems and to utilize efficiently the FPGA architecture
1. Simulator: Modelsim 
2. Synthesizer and Place & Route: Quartus Prime 
3. Course book (including labs)
Next course will be held on:

April 10-14

May 15-17 + 22-23