ALTERA FPGA Design: The Complete Suite

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This course provides all necessary theoretical and practical know-how to design ALTERA FPGA/CPLD using VHDL standard language.
The course intention is to train computer and electronics engineers from scratch to practical work level.
The course goes into great depth, and touches upon every aspect of the standard and FPGA design with directly connected to the topics needed in the industry today.
The course combines 50% theory with 50% practical work in every meeting. The practical labs cover all the theory and also include practical digital design.
The course begins with an overview of the current programmable logic devices and their capabilities, continues with an in-depth study of VHDL language with all of its structures, involves writing test-bench programs and employ a simulation tool. The course also teaches how to employ correct coding-style for synthesis, design pipeline circuits for high frequency, optimize arithmetic/logic operations, insert timing constraints, analyze design problems and solve them, design multi-clock domains in FPGA and synchronization circuits.
The course continues with ALTERA FPGA architecture and how to utilize it for best performance/area/power.
At the end of the course engineers will feel confidence to design a new FPGA project.
Course Duration : 15 days
1. Become familiar with ALTERA FPGA and CPLD families and their capabilities
2. Understand the design process from specification up to programming and final verification on board
3.  Implement combinational and sequential processes
4.  Build a hierarchy (bottom-up and top-down)
5.  Write test-benches
6.  Write generic code for design reuse
7.  Understand coding style considerations for synthesis
8.  Synthesize multi-files projects
9.  Become familiar and insert timing constraints
10. Become familiar with bad coding style and their remedies
11. Employ efficient design methodologies for high frequency or minimal area
12. Configure and embed IP in the design
13. Produce and analyze reports
14. Identify and fix timing issues
15. Utilize the FPGA architecture in the most efficient way with proper RTL coding style
16. Design pipeline circuits with an emphasis on latency and throughput
17. Close design timing and optimize critical path
18. Configure and use PLL in the design
19. Design a reliable multi-clock domains system with synchronization circuits
20. Design a reliable reset circuits
21. Optimize the design with synthesis and Place & Route tools
22. Program the FPGA on board
Hardware engineers who would like start developing FPGA or CPLD
System engineers who would like to upgrade their professional skills
1. Simulator: Modelsim 
2. Synthesizer and Place & Route: Quartus Prime
3. ALTERA Evaluation board
4. Course book (including labs)
Next course will be held on:
This course is a full training program for high-tech companies