Accelerate System Performance with Altera SoC

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This course provides all theoretical and practical know-how to design ALTERA SoC devices under Quartus II software.
The course combines 60% theory and 40% practical work on ALTERA SoC evaluation boards.
The course starts with SoC families overview and their capabilities, continues with deep methodic training of the SoC architecture.
The course teaches the HPS architecture and its building blocks, how to manage SoC system, how to configure system based on SoC, how to transfer data through the Bus system and internal interconnect, how to connect external memories, how to build a system with Qsys, how to handle interrupts and how to use efficiently pin muxing.
The second part of the course focuses on practical use of simulation models (BFMs), creating SoC test-benches, and performing different boot processes with and without operating system.
The course ends with SoC debug interfaces overview, how and when to use them, cross-triggering between CPUs and FPGAs and how to use the system console manager.
Course Duration : 3 days
1. Become familiar with ALTERA SoC families, their capabilities and when to use them
2. Understand SoC design hardware and software flow from specification to programming and final verification on the board
3. Integrate IPs into the SoC design (also custom peripherals)
4. Configure the SoC system (clocks, PLLs, Resets, Peripherals)
5. Use efficiently the Qsys tool
6. Use Bus Functional Models (BFMs) to simulate SoC behavior
7. Program and use SignalTap II to verify the SoC functionality
8. Understand and choose the right Boot scheme
9. Handle Interrupts using the Generic Interrupt Controller (GIC)
10. Connect external memories to the SoC
Hardware and system engineers who would like to design with ALTERA SoC technology
1. Simulator: Modelsim 
2. Synthesizer and Place & Route: Quartus Prime
3. ALTERA Cyclone V SoC  Evaluation board
4. Course Book (including labs)
Next course will be held on:

April 3-5

June 6-8