Verilog Essentials Simulation & Synthesis

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This course provides all necessary theoretical and practical know-how to design programmable logic devices using Verilog standard language.

The course goes into great depth, and touches upon every aspect of the standard with directly connected to the topics needed in the industry today.
The course combines 50% theory with 50% practical work in every meeting. The practical labs cover all the theory and also include practical digital design. 


The course begins with an overview of the current programmable logic devices and their capabilities, continues with an in-depth study of Verilog language with all of its structures, involves writing test-bench programs and employ a simulation tool. The course ends with a synthesis overview and emphasizes the difference between testing code and synthesizable code.


Course Duration : 5 days




1.       Become familiar with FPGA and CPLD families and their capabilities


2.       Understand the design process from specification up to programming and final
           verification on board

3.       Implement combinational and sequential processes


4.       Build a hierarchy (bottom-up and top-down)


5.       Write test-benches


6.       Write generic code for design reuse


7.       Understand coding style considerations for synthesis








Hardware engineers who would like start developing FPGA or CPLD

System engineers who would like to upgrade their professional skills

1.       Simulator: Modelsim          
2.       Synthesizer and Place & Route: Quartus Prime    

3.       Demonstration on ALTERA Evaluation board

4.     Course book (including labs)



Next course will be held on:

May 15,16,22,23,24