VHDL 2008 the Newest Standard

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This course introduces the new and changed features of VHDL-2008, in order to improve and enhance hardware engineer´s skills.
 
The course goes into great depth and teaches the advanced features of the VHDL-2008 language through code examples, shows how they improve the language as a tool for design and verification, and guides how to employ them in new designs.
 
The course combines 50% theory with 50% practical work in every meeting.
 
The practical labs cover all the theory and also include practical digital design.
 
This course also enriches digital engineers with many years of experience.
 
Course Duration : 3 days
1. Write generic  models at the highest level for synthesis
 
2. Use generic functions and procedures for synthesis include operator and function overloading
 
3. Write VHDL programs with VHDL2008 standard
 
4. Write advanced test-benches using VHPI and PSL
 
5. Apply advanced arithmetic/logic operations on arrays and scalars
 
6. Write advanced test-benches that read and write from/to files
 
7. Become familiar with the expand IEEE Packages
 
8. Advanced use of TYPE
Hardware engineers who develop FPGAs and would like to enhance their skills, in order to become experts with VHDL language for design and verification
1. Simulator: Modelsim 
 
2. Synthesizer and Place & Route: Quartus Prime

3. Course book (including labs)
Next course will be held on:
June 26-28