Fast & Optimized Arithmetic Circuits

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This 1-day seminar provides unique opportunity to be exposed to the mathematic techniques for high frequency and minimal area.
 
The seminar begins with an overview of today FPGAs mathematics capabilities, continues with fast architectures for add, subtract, count, multiply, divide, and signed operations.
 
The seminar also focuses on implementation for synthesis taking area and frequency constraints into consideration.
 
The seminar combines 50% theory with 50% practical work. 
 
Seminar Duration : 1 day
1. Write an efficient RTL code and maximize FPGA architecture utilization for arithmetic circuits
 
2. Design pipeline circuits with an emphasis on latency and throughput considerations
 
3. Design an efficient arithmetic circuits for synthesis with an emphasis on algorithms
Hardware engineers who develop FPGAs and would like to enhance their skills, expand their knowledge, and utilize the FPGA architecture in the most efficient way
1. Simulator: ModelSim 
 
2. Synthesizer and Place & Route: Quartus Prime
 
3. Course book (including labs)
Next course will be held on:
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