FPGA Low Power Design

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This 1-day seminar provides all necessary know-how and considerations needed to design FPGAs for low power requirements.
The seminar exposes the practical techniques that can be employed to optimize FPGAs for low power consumption.
The seminar covers the clock tree structure, static and dynamic power calculations, optimizations in synthesis and Place & Route tools, clocks management, decrease internal RAMs power consumption, I/O design guidelines, retiming techniques, use dynamically on device terminations, use power analysis tools, generate reports and analyze them.
The seminar combines 50% theory with 50% practical work. 
Seminar Duration : 1 day
1. Become familiar with the considerations for FPGA low power design
2. Efficiently manage the workspace and R&D resources
3. Become familiar with power architecture design and considerations
4. Decrease internal RAM power consumption
5. Efficiently manage clocks
6. Calculate and analyze power
7. Become familiar with I/O design guidelines
Hardware engineers who develop FPGAs where power consumption is a major requirement
1. Simulator: ModelSim 
2. Synthesizer and Place & Route: Quartus Prime
3. Course book (including labs)
Next course will be held on:
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