Implementing, Simulating & Debugging External Memory Interfaces

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This course teaches the Altera´s high-performance external memory interface IP, and how to implement an interface with the Quartus II software.
The course includes lecture and lab exercises to learn the design flows, options, and challenges in creating such an interface.
The class focuses on implementing DDR3 interfaces using Stratix series devices including specific information about Stratix V implementations.
However, DDR/DDR2, LPDDR2, RLDRAM II/3, SRAM, & QDRII/+ memory types, as well as other device families, such as the Cyclone V & Arria V series devices will also be touched upon.
The participant will create & simulate a fully functional DDR3 SDRAM controller with auto-calibrating PHY block (UniPHY) interface running at up to 800 MHz.
This course also enriches digital engineers with many years of experience.
Course Duration : 2 days
1. Implement external memory interfaces, including hard memory controllers in Cyclone V & Arria V devices
2. Parameterize & generate high performance controller & PHY (UniPHY) using the MegaWizard plug-in manager
3. Verify controller functionality with ModelSim tool
4. Close timing
5. Connect your own logic to the controller or connect your own controller to UniPHY
6. Use the external memory interface Toolkit to analyze & report memory calibration & margin
7. Implement multiple controllers
Hardware engineers who develop FPGAs and would like interfacing to high speed external memories such as DDR3
1. Synthesizer and Place & Route: Quartus Prime
2. Simulator: ModelSim
3. Course book (including labs)
Next course will be held on:
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