Advanced ALTERA FPGA Design

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The first part covers advanced timing closure problems, analysis and solutions.
 
The second part covers Qsys tool that is used for building systems in FPGA.
 
The third part covers high speed external memory interfaces design such as DDR3.
 
The fourth part covers FPGA design optimizations such as LogicLock and incremental compilation.
 
The course combines 50% theory with 50% practical work in every meeting. The practical labs cover all the theory and also include practical digital design.
 
At the end of the course FPGA engineers will enhance their skills that needed for complex and high speed designs.
 
Course Duration : 8 days
1. Design timing closure methodology like ALTERA experts
 
2. Analyze and solve timing problems with Quartus II software
 
3. Efficiently manage device clock resources and PLLs
 
4. Use TimeQuest advanced features
 
5. Build a system with Qsys
 
6. Implement high speed memory interfaces such as DDR3
 
7. Optimize FPGA design with LogicLock and incremental compilation
FPGA engineers who would like to enhance their skills and design complex and high speed FPGA projects
1. Simulator: Modelsim
 
2. Synthesizer and Place & Route: Quartus Prime
 
3. ALTERA Evaluation board
 
4. Course book (including labs)
Next course will be held on:
This course is a full training program for high-tech companies