VHDL Expert Simulation & Synthesis

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This course expands the theoretical and practical know-how to write synthesizable and advanced test-benches through VHDL standard language.
The course goes into great depth and teaches the advanced features of the VHDL language to design complex projects, sophisticated test-bench, full generic design for reuse purposes, and advanced use of functions and procedures.
In addition, the course teaches how to implement software algorithm in an efficient way and how to apply resource sharing techniques in order to decrease area or increase frequency.
The course emphasizes the most recent updates of the VHDL2008 standard, and guides how to employ them in new designs.
The course combines 50% theory with 50% practical work in every meeting. The practical labs cover all the theory and also include practical digital design.
This course also enriches digital engineers with many years of experience.
Course Duration : 5 days
1. Write generic  models at the highest level for synthesis
2. Use of pointers (Access type) to generate linked-lists for advanced test-bench programs
3. Use generic functions and procedures for synthesis include operator and function overloading
4. Write VHDL programs with VHDL2008 standard
5. Write advanced test-benches that read and write from/to files
6. Use functionality sharing technique for most efficient code for synthesis
7. Implement efficiently software algorithms in hardware
Hardware engineers who develop FPGAs and would like to enhance their skills, in order to become experts with VHDL language
1. Simulator: Modelsim 
2. Synthesizer and Place & Route: Quartus Prime

3. Course book (including labs)
Next course will be held on:

June 19,20,21,26,27