Parallel Computing with OpenCL for Altera FPGAs

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OpenCL is a standard for writing parallel programs for heterogeneous systems. 
In the FPGA environment, OpenCL constructs are synthesized into custom logic. 
This course introduces the basic concepts of parallel computing. 
It covers the constructs of the OpenCL standard & Altera flow that automatically converts kernel C code into hardware that interacts with the host. 
In hands-on labs, you´ll write programs to run on both the CPU & FPGA.In addition, the course covers the optimization techniques needed to implement a high performance OpenCL solution on an FPGA using the Altera SDK for OpenCL. 
We will discuss good coding design practices, ways to improve data processing efficiency, memory access efficiencies, and host side optimizations. 
We will also focus on Altera SDK for OpenCL specific features that can significantly improve OpenCL performance on FPGAs compared to other platforms.

Course Duration : 3 days
1. Describe high-level parallel computing concepts and challenges
2. Understand the advantages of using Altera´s OpenCL solution
3. Know the basics of the OpenCL standard
4. Write simple programs in OpenCL
5. Compile and run OpenCL programs using the Altera solution
6. Use good coding design practices to implement a high performance OpenCL FPGA system
7. Apply multiple methods to improve data processing efficiency of OpenCL kernels
8. Reduce host-device communication overhead by improving memory access efficiencies and using       channels
9. Understand Altera specific features that will significantly boost the performance of an OpenCL solution
Hardware and software engineers who develop and work with parallel algorithms and computationally intense applications for Altera FPGAs
1. Synthesizer and Place & Route: Quartus Prime
2. Altera SDK for OpenCL
3. Microsoft® Visual C++® 2010 (Express)
4. Windows® SDK 7.1
5. Intel® SDK for OpenCL™ Application 2012
6. Course book (including labs)
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