Synchronization Circuits Design in Altera FPGAs

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This course focuses on synchronization circuits design in Altera FPGAs using Quartus software to measure MTBF.

The course starts with the motivation to increase circuit reliability by understanding synchronization circuit role for cross clock domain design.

The course continues with deep dive exposure to the most advanced synchronization techniques for various use cases, such as   and choosing the right solution for your specific design.

The course covers also the synchronization circuit for reset.

The course ends with the flow in Quartus II to make sure the software identify your synchronization circuits, then analyze their reliability (using circuits for cross clock domain designs MTBF calculations) in TimeQuest.

The course has hands-on lab that encapsulate all theory into one final practical work, where the participant will design a handshake synchronization protocol.

Course Duration : 1 day

1. Increase circuit reliability and performance by applying synchronous design techniques
2. Be familiar with metastability formula
3. Understand the synchronization circuits role in synchronous design

4. Choose the right synchronization solution for your design
5. State advantages and disadvantages of synchronous and asynchronous reset

6. Apply a synchronization circuit for an asynchronous reset

7. Design synchronization circuits for multiple clock domain designs

FPGA engineers who would like to enhance their skills and design reliable multi-clock domains FPGA projects, and analyze their solution in TimeQuest.
1. Simulator: Modelsim

2. Synthesizer and Place & Route: Quartus Prime

3. Course book (including labs)
Next course will be held on:

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