Design Secure Solutions with Altera Arria 10

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This course will teach you how to design secure solutions and prevent reverse engineering to your FPGA based products.

The course provides an in-depth overview of the key points that a hardware/software developer has to take into his considerations while developing protected/secured software for ARM processors and HDL algorithms implementation in the FPGA fabric.

The course also includes practical labs in which the hardware/software engineer can experience with the security features.

The course starts with an overview of the security challenges and the impact of security breaches to businesses, IoT security challenges, application security, hash functions, and encryption algorithms.

The course covers the Arria 10 family security and protection features to secure the design against copying, reverse engineering, side channel attacks and tampering, such as AES-256, fuses, DPA resistant decryptor, symmetric and assymetric authentication, Chip ID, JTAG secure mode, chip core zeroize, and Verify protect, Hard ERAM ECC, SEU mitigation & configuration error detection, and tamper protection bit.

The course continues with an in-depth security protocol flow design, which parts should be designed in the FPGA fabric and which in ARM according to different use cases.

At the end of this course, the participant will enhance his understanding of the Arria 10 architecture security features, the possible threats, efficiently use the device security and protection features.

Course Duration : 2 days

1. Become familiar with security challenges today and in near future
2. Become familiar with security and protection methods and algorithms
3. Become familiar  with the Arria 10 family security features
4. Develop secure boot trust chain
5. Protect code and data from unauthorized accesses
6. Encrypt data with AES-256 hardware accelerator
7. Understand security configuration impact on debug and external bus capabilities
8. Understand the security protocol flow and hardware-software requirements

FPGA engineers who would like to secure and protect their solutions from being hacked or copied.

1. ARM DS5 Altera Edition
2. Synthesizer and Place & Route: Quartus Prime 
3. Course book (including labs)
Next course will be held on:

April 13-14

June 15-16