Design Secure Solutions with Altera MAX 10

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This course will teach you how to design secure solutions for IoT end nodes using Altera MAX 10 FPGA. 
The course provides an in-depth overview of the key points that a hardware/software developer has to take into his considerations while developing protected/secured software for NIOS II or/and HDL algorithms implementation in the FPGA fabric.
The course also includes practical labs in which the hardware/software engineer can experience with the security features on Max 10 evaluation board.
The course starts with an overview of the security challenges and the impact of security breaches to businesses, IoT security challenges, application security, hashing functions, and encryption algorithms.
The course covers the MAX 10 family security and Flash protection features to secure the design against copying, reverse engineering, and tampering, such as AES-128, Chip ID, JTAG secure mode, dual boot, and Verify protect, SEU mitigation & configuration error detection, and tamper protection bit. 
The course continues with an in-depth security protocol flow design, which parts should be designed in the FPGA fabric and which in NIOS II according to different use cases.The labs demonstrate Flash data and code protection, as well as configuring and using of cryptography ciphers in number of modes as described in 800-38 NIST standards.

At the end of this course, the participant will enhance his understanding of the MAX 10 architecture security features, the possible threats, efficiently use the cryptographic accelerator, Flash security and protection features.

Course duration : 1 day

1.   1. Become familiar with security challenges today and in near future

2.   2. Become familiar with security and protection methods and algorithms

3.   3. Become familiar  with the MAX 10 family security features 

4.   4. Protect Flash code and data from unauthorized accesses

5.   5.  Encrypt data with AES-128 hardware accelerator

6.   6. Understand security configuration impact on debug and external bus capabilities

7.   7. Understand the security protocol flow and hardware-software requirements

FPGA engineers who would like to secure and protect their solutions from being hacked or reverse engineered.
1. Nios II EDK
2. Synthesizer and Place & Route: Quartus Prime 
3. Course book (including labs)
4. MAX 10 EVM
Next course will be held on:
 Please contact us.