Altera FPGA Design for High Productivity

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This course provides all practical know-how needed to achieve higher productivity in Intel FPGAs.
The course goes into great depth and touches upon various aspects of the design flow and the daily problems in the industry such as compilation time, resource utilization and debugging.
The course provides practical tools and design methods for engineers in order to increase their productivity by finish their projects quicker with best results.

Course duration : 2 days
1. Understand resource utilization reports for Altera FPGAs families

2. Design efficient HDL code for the best resource utilization

3. Decrease Quartus compilation time 

Digital hardware engineers and FPGA team leaders, who would like to enhance their FPGA skills and achieve higher productivity in their FPGA design
1. Simultor: Modelsim

2. Synthesizer and Place & Route: Quartus Prime

3. Course book (including labs) 

Next course will be held on: