Building Interfaces with Arria 10 High-Speed Transceivers

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In this course, you will learn how you can build high-speed, gigabit interfaces using the 20-nm embedded transceivers found in Arria 10. 

You will be introduced to the transceiver architecture and how the transceivers are configured to support various high-speed protocols. 
You will learn how to optimize and debug both the digital and analog sections of your transceiver design. You will gain an understanding of the transceiver reconfiguration controller and how you can use it to fine tune transceiver settings and add flexibility to your transceiver design.Lastly, you will be made aware of common "gotchas” that occur in transceiver designs and what steps you can take to avoid them.

The course contains hands-on labs to experience with Arria 10 transceiver IP cores configuration, simulation, using the transceiver Toolkit (optional), and enabling Arria 10 transceiver reconfiguration in the Native PHY IP core.

Course Duration: 2 days
1. Implement high-speed serial protocols in Altera 20-nm embedded transceivers
2. Optimize analog settings to improve behavior using Altera tools
3. Employ transceiver reconfiguration to dynamically change transceiver behavior in-system
4. Improve transceiver usage and avoid transceiver design issues by applying an understanding of device architecture to design situations
Hardware engineers who develop with Arria 10 and would like to build gigabit interfaces 
1. Synthesizer and Place & Route: Quartus Prime
2. Course book (including labs)
3. Stratix V or Arria 10 Evaluation board (optional)
Next course will be held on: