Performance Optimization with Stratix 10 HyperFlex Arachitecture

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Altera Stratix 10 introduces its new architecture, HyperFlex along with 14nm Intel Tri-Gate technology.
The new architecture allows FPGA designers to control their design performance by using registers throughout the core fabric, which provides a better approach to retiming, pipelining and optimization, in order to achieve timing closure faster.
This course provides all practical know-how needed to achieve higher productivity in Altera Stratix 10 FPGAs.
The course goes deep into the HyperFlex architecture and expose all Quartus Prime features, design new methodologies and new tools such as Fast Forward Compile.
The course provides practical tools and design methods for engineers in order to increase their productivity by finish their projects quicker with best results.

Course Duration: 2 days
1. Become familiar with Altera Stratix 10 HyperFlex architecture
2. Use Quartus Prime features to take advantage of Stratix 10 HyperFlex architecture
3. Speculate design performance gains using Fast Forward Compile feature
4. Employ Hyper-Retiming strategy to improve design performance
5. Employ Hyper-Pipelining strategy to improve design performance
Digital hardware engineers and FPGA team leaders, who would like to design with Stratix 10 FPGA and achieve higher productivity in their design
1. Synthesizer and Place & Route: Quartus Prime Standard/Pro Edition
2. Course book (including labs) 
Next course will be held on:
 November 2016
Please contact us for the exact dates