UVM Fundamentals

This 5-days course designed for ASIC & FPGA verification engineers that would like to use the SystemVerilog language and UVM methodology to verify deeply digital designs.SystemVerilog is a significant new enhancement to Verilog and includes major extensions into abstract design, testbench, formal, and C-based APIs.  

SystemVerilog also defines new layers in the Verilog simulation strata.
These extensions provide significant new capabilities to the verification engineer, such as Object-Oriented Programming (OOP), randomization, assertions, packages, queues, dynamic & associative arrays, interfaces and functional coverage.
These new features allow better teamwork and co-ordination between different project members. 

Universal Verification Methodology (UVM) is a standardized methodology for verifying digital designs and SoC.
It is built on top of SV language and consists of set of standards, tools, and APIs for design verification.
UVM helps companies develop modular, reusable, and scalable test benches that can be deployed across multiple projects.

The first day introduces the essential SystemVerilog concepts & constructs that are critical for the UVM part and it includes hands-on labs to practice these concepts.
The first part covers OOP, functional code coverage, assertion and randomization.
The next 4-days introduce the UVM and its structure, then covers the UVM library, reporting mechanism, factory, TLM, configuration database, phases, hierarchy, test and testbench top.
Then the training covers how to generate stimulus with sequences and virtual sequences as well as RAL.
Extensive practical labs are integrated during the training to make sure that the participant understand the flow, structure and concept of each verification building block.